TSB43AB23

Product Summary

The TSB43AB23 is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification (Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification (Release 1.1). It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB23 provides three 1394 ports that have separate cable bias (TPBIAS). The TSB43AB23 also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.

Parametrics

TSB43AB23 absolute maximum ratings: (1)Supply voltage range: REG18: –0.2 V to 2.2 V; (2)AVDD: –0.3 V to 4.0 V; (3)DVDD: –0.3 V to 4.0 V; (4)PLLVDD: –0.3 V to 4.0 V; (5)VDDP: –0.5 V to 5.5 V; (6)Input voltage range for PCI, VI, PHY, and Miscellaneous: –0.5 to VDD + 0.5 V; (7)Output voltage range for PCI, VO, PHY, and Miscellaneous : –0.5 to VDD + 0.5 V; (8)Input clamp current, IIK (VI＜0 or VI＞VDD): ±20 mA; (9)Output clamp current, IOK (VO＜0 or VO＞VDD): ±20 mA; (10)Electrostatic discharge: HBM: 2 kV; (11)Continuous total power dissipation: See Dissipation Rating Table; (12)Operating free-air temperature, TA: 0 to 70℃; (13)Storage temperature range, Tstg: –65 to 150℃; (14)Lead temperature 1,6 mm (1/16 inch) from cage for 10 seconds : 260℃.

Features

TSB43AB23 features: (1)Fully compliant with 1394 Open Host Controller Interface Specification (Release 1.1); (2)Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus?and IEEE Std 1394a-2000; (3)Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394; (4)Compliant with Intel Mobile Power Guideline 2000; (5)Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume; (6)Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer, and inactive ports powered down; (7)Ultralow-power sleep mode; (8)Three IEEE Std 1394a-2000 fully compliant cable ports at 100M bits/s, 200M bits/s, and 400M bits/s; (9)Cable ports monitor line conditions for active connection to remote node; (10)Cable power presence monitoring; (11)Separate cable bias (TPBIAS) for each port; (12)1.8-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments; (13)Physical write posting of up to three outstanding transactions; (14)PCI burst transfers and deep FIFOs to tolerate large host latency; (15)PCI_CLKRUN protocol; (16)External cycle timer control for customized synchronization; (17)Extended resume signaling for compatibility with legacy DV components; (18)PHY-link logic performs system initialization and arbitration functions; (19)PHY-link encode and decode functions included for data-strobe bit level encoding; (20)PHY-link incoming data resynchronized to local clock; (21)Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s; (22)Node power class information signaling for system power management; (23)Serial ROM interface supports 2-wire serial EEPROM devices; (24)Two general-purpose I/Os; (25)Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std 1394a-2000 features; (26)Fabricated in advanced low-power CMOS process; (27)Isochronous receive dual-buffer mode; (28)Out-of-order pipelining for asynchronous transmit requests; (29)Register access fail interrupt when the PHY SCLK is not active.

Diagrams