(China (Mainland))
Product Summary
The HY5DU561622DTP-J is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The HY5DU561622DTP-J offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels of the HY5DU561622DTP-J are compatible with SSTL_2.
Parametrics
HY5DU561622DTP-J absolute maximum ratings: (1)Ambient Temperature: 0 ~ 70℃; (2)Storage Temperature: -55 ~ 125℃; (3)Voltage on Any Pin relative to VSS: -0.5 ~ 3.6 V; (4)Voltage on VDD relative to VSS: -0.5 ~ 3.6 V; (5)Voltage on VDDQ relative to VSS: -0.5 ~ 3.6 V; (6)Output Short Circuit Current: 50 mA; (7)Power Dissipation: 1 W; (8)Soldering Temperature: 260 ·10 ℃·sec.
Features
HY5DU561622DTP-J features: (1)All inputs and outputs are compatible with SSTL_2 interface; (2)Fully differential clock inputs (CK, /CK) operation; (3)Double data rate interface; (4)Source synchronous - data transaction aligned to bidirectional data strobe (DQS); (5)x16 device has two bytewide data strobes (UDQS,LDQS) per each x8 I/O; (6)Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ); (7)On chip DLL align DQ and DQS transition with CK transition; (8)DM mask write data-in at the both rising and falling edges of the data strobe; (9)All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock; (10)Programmable CAS latency 1.5, 2, 2.5 and 3 supported; (11)Programmable burst length 2 / 4 / 8 with both sequential and interleave mode; (12)Internal four bank operations with single pulsed /RAS; (13)tRAS Lock-out function supported; (14)Auto refresh and Self refresh supported; (15)8192 refresh cycles / 64ms; (16)JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch (Lead free package); (17)Full and Half strength driver option controlled by EMRS.
Diagrams
