(China (Mainland))
Product Summary
The H57V2562GTR-75C is a 268,435,456 bit CMOS synchronous DRAM, ideally suited for the consumer memory applications which requires large memory density and high bandwidth. It is organized as 4banks of 4,194,304 x 16 I/O. Synchronous DRAM is a type of DRAM which operates in synchronization with input clock. The H57V2562GTR-75C Hynix Synchronous DRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data in synchronization with the input clock (CLK). The address lines are multiplexed with the Data Input/ Output signals on a multiplexed x16 Input/ Output bus. All the commands are latched in synchronization with the rising edge of CLK.
Parametrics
H57V2562GTR-75C absolute maximum ratings: (1)Ambient temperature, TA: 0 ~ 70℃; (2)Storage temperature, TSTG: -55 ~ 125℃; (3)Voltage on any pin relative to VSS, VIN, VOUT: -1.0 ~ 4.6 V; (4)Voltage on VDD supply relative to VSS, VDD, VDDQ: -1.0 ~ 4.6 V; (5)Short circuit output current IOS: 50 mA; (6)Power dissipation, PD: 1W.
Features
H57V2562GTR-75C features: (1)Standard SDRAM Protocol; (2)Internal 4bank operation; (3)Power supply voltage: VDD = 3.3V, VDDQ = 3.3V; (4)All device pins are compatible with LVTTL interface; (5)Low voltage interface to reduce I/O power; (6)8,192 refresh cycles / 64ms; (7)Programmable CAS latency of 2 or 3; (8)Programmable burst length and burst type; (9)Commercial temp: 0 ~ 70℃ Operation; (10)Package type: 54_Pin TSOPII; (11)This product is in compliance with the directive pertaining of RoHS.
Diagrams
