XC7372-10PC84C

Product Summary

The XC7372-10PC84C EPLD employs a unique Dual-Block architecture, which provides high speed operations via Fast Function Blocks and/or high density capability via High Density Function Blocks. Fast Function Blocks (FFBs) of the XC7372-10PC84CEPLD provide fast, pin-to-pin speed and logic throughput for critical decoding and ultra-fast state machine applications. High-Density Function Blocks (FBs) of the XC7372-10PC84CEPLD provide maximum logic density and system-level features to implement complex functions with pre-dictable timing for adders and accumulators, wide functions and state machines requiring large numbers of product terms, and other forms of complex logic.

Parametrics

XC7372-10PC84C absolute maximum ratings: (1)Total Number of Arrays: 8; (2)Total # of Logic Cell (macros): 72; (3)# of Cells (macros) Per Array: 9; (4)Total Number of Product Terms: 432; (5)# of Product Terms Per Array: 57; (6)# of Inputs From Switch Matrix: 21; (7)Number of Input Terminals: 12; (8)Number of I/O Terminals: 37; (9)Number of Output Terminals: 23; (10)Digital Input V Max (V): 7.0; (11)I(IL) Maximum (A): 10u; (12)@V(IL) (test) (V): 0; (13)Output Config: 3-State; (14)Output Logic Polarity: Programmab; (15)3-State Voltage Maximum: 7.0; (16)VOL Max.: 0.5; (17)@Iol (A): 24m; (18)t(PLH) Maximum (S): 10n; (19)Minimum Operating Temp (шC): 0; (20)Maximum Operating Temp (шC): 70; (21)Package Style: QCC-J; (22)Mounting Style: S; (23)# Pins: 68.

Features

XC7372-10PC84C features: (1)High-performance Erasable Programmable Logic Devices (EPLDs): 5 / 7.5 ns pin-to-pin speeds on all fast inputs; Up to 167 MHz maximum clock frequency; (2)Advanced Dual-Block architecture: Fast Function Blocks; High-Density Function Blocks; (3)100% interconnect matrix; (4)High-speed arithmetic carry network: 1 ns ripple-carry delay per bit; 43 to 61 MHz 18-bit accumulators; (5)Multiple independent clocks; (6)Each input programmable as direct, latched, or registered; (7)High-drive 24 mA output ; (8)I/O operation at 3.3 V or 5 V; (9)Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V; (10)Power management options; (11)Multiple security bits for design protection; (12)Supported by industry standard design and verification tools; (13)100% PCI compliant instruments.

Diagrams