Product Summary
The sn74lv8151nt is a 10-bit universal Schmitt-trigger buffer with 3-state outputs. The sn74lv8151nt is designed for 2-V to 5.5-V VCC operation. The logic control (T/C) pin of the sn74lv8151nt allows the user to configure Y1 to Y8 as noninverting or inverting outputs. When output-enable (OE) input is low, the sn74lv8151nt passes data from Dn to Yn. When OE is high, the Y outputs of the sn74lv8151nt are in the high-impedance state. The sn74lv8151nt is fully specified for partial-power-down applications using Ioff.
Parametrics
sn74lv8151nt absolute maximum ratings: (1) Supply voltage range, VCC: -0.5 to 7V; (2) Input voltage range, VI: -0.5 to 7V; (3) Voltage range applied to any output in the high-impedance or power-off state, VO: -0.5 to 7V; (4) Output voltage range, VO: -0.5 to Vcc +0.5V; (5) Input clamp current, IIK (VI <0) : -20mA; (6) Output clamp current, IOK (VO<0) : -50mA; (7) Continuous output current, IO (VO= 0 to VCC) : ±35mA; (8) Continuous current through VCC or GND: ±70mA; (9) Storage temperature range, Tstg: -65 to +150°C.
Features
sn74lv8151nt features: (1) 2-V to 5.5-V VCC Operation; (2) Max tpd of 15ns at 5V; (3) Schmitt-Trigger Inputs Allow for Slow Input Rise/Fall Time; (4) Polarity Control for Y Outputs Selects True or Complementary Logic; (5) Typical VOLP (Output Ground Bounce) <0.8V at Vcc=3.3V, TA=25°C; (6) Typical VOHV (Output VOH Undershoot) >2.3 V at Vcc=3.3C, TA=25°C; (7) Ioff Supports Partial-Power-Down Mode Operation; (8) Supports Mixed-Mode Voltage Operation on All Ports; (9) Latch-Up Performance Exceeds 250 mA Per JESD 17; (10) ESD Protection Exceeds JESD 22.
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
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SN74LV8151NT |
Texas Instruments |
Buffers & Line Drivers 10-Bit Univ Schmitt- Trgr Bfr W/3-St Otpt |
Data Sheet |
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SN74LV8151NTE4 |
Texas Instruments |
Buffers & Line Drivers 10-Bit Univ Schmitt- Trgr Bfr W/3-St Otpt |
Data Sheet |
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