(China (Mainland))
Product Summary
The MT46V32M8TG-6TG is a Double Data Rate (DDR) SDRAM uses a double data rate architecture to achieve high-speed operation. The MT46V32M8TG-6TG architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM effectively consists of a single 2n-bit-wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one half-clock-cycle data transfers at the I/O pins.
Parametrics
MT46V32M8TG-6TG absolute maximum ratings: (1)VDD supply voltage relative to VSS: -1V to 3.6V; (2)VDDQ supply voltage relative to VSS: -1V to 3.6V; (3)VREF and inputs voltage relative to VSS: -1V to 3.6V; (4)I/O pins voltage relative to VSS: -0.5V to VDDQ +0.5V; (5)Storage temperature (plastic): -55 to 150℃; (6)Short circuit output current: 50 mA.
Features
MT46V32M8TG-6TG features: (1)VDD = 2.5V ±0.2V; VDDQ = 2.5V ±0.2V; (2)VDD = 2.6V ±0.1V; VDDQ = 2.6V ±0.1V (DDR400)1; (3)Bidirectional data strobe (DQS) transmitted/received with data, that is, source-synchronous data capture (x16 has two-one per byte); (4)Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle; (5)Differential clock inputs (CK and CK#); (6)Commands entered on each positive CK edge; (7)DQS edge-aligned with data for READs; centeraligned with data for WRITEs; (8)DLL to align DQ and DQS transitions with CK; (9)Four internal banks for concurrent operation; (10)Data mask (DM) for masking write data (x16 has two-one per byte); (11)Programmable burst lengths (BL): 2, 4, or 8; (12)Auto refresh; (13)64ms, 8192-cycle; (14)Longer-lead TSOP for improved reliability (OCPL); (15)2.5V I/O (SSTL_2-compatible); (16)Concurrent auto precharge option supported; (17).tRAS lockout supported (tRAP = tRCD).
Diagrams
