(China (Mainland))
Product Summary
The K4H561638N-LCB3 is a 268,435,456 bits of double data rate synchronous DRAM organized as 4x 4,194,304 words by 4/8/16bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the K4H561638N-LCB3 to be useful for a variety of high performance memory system applications.
Parametrics
K4H561638N-LCB3 absolute maximum ratings: (1)Voltage on any pin relative to VSS: VIN, VOUT: -0.5 ~ 3.6 V; (2)Voltage on VDD & VDDQ supply relative to VSS: VDD, VDDQ: 1.0 ~ 3.6 V; (3)Storage temperature: TSTG: -55 ~ +150 °C; (4)Power dissipation: PD: 1 W; (5)Short circuit current: IOS: 50 mA.
Features
K4H561638N-LCB3 features: (1)VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V; (2)Double-data-rate architecture; two data transfers per clock cycle; (3)Bidirectional data strobe [DQS] (x4,x8)& [L(U)DQS] (x16); (4)Four banks operation; (5)Differential clock inputs(CK and CK); (6)DLL aligns DQ and DQS transition with CK transition; (7)MRS cycle with address key programs: Read latency : DDR266(2, 2.5 Clock), DDR33 : (2.5 Clock), DDR400(3 Clock), Burst length (2, 4, 8), Burst type (sequential & interleave); (8)All inputs except data & DM are sampled at the positive going edge of the system clock(CK); (9)Data I/O transactions on both edges of data strobe; (10)Edge aligned data output, center aligned data input; (11)LDM,UDM for write masking only (x16); (12)DM for write masking only (x4, x8); (13)Auto & Self refresh; (14)7.8us refresh interval(8K/64ms refresh); (15)Maximum burst refresh cycle : 8; (16)66pin TSOP II Lead-Free & Halogen-Free package; (17)RoHS compliant.
Diagrams
