HY5DV641622AT-36

Synchronous DRAM, 3.3V, 50 mA, 1 W, TSOP

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Price:: US $1.70~2.00 / piece [Get Latest Price]

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1 ~ 10 :	2.00 / Piece
20 ~ 100 :	1.70 / Piece

PartNumber:: HY5DV641622AT-36

Brand:: Hynix Semiconductor - Hynix | Pack: TSOP | D/C: 07+

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Products Upload time: 2013-08-11

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Part Number:HY5DV641622AT-36
US $1.70 - 2.00
Quantity:

piece

Product Summary

The HY5DV641622AT-36 is a 67,108,864-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The HY5DV641622AT-36 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels of the HY5DV641622AT-36 are compatible with SSTL_2.

Parametrics

HY5DV641622AT-36 absolute maximum ratings: (1)Ambient Temperature: 0 ~ 70℃; (2)Storage Temperature: -55 ~ 125℃; (3)Voltage on Any Pin relative to VSS: -0.5 ~ 3.6 V; (4)Voltage on VDD relative to VSS: -0.5 ~ 3.6 V; (5)Voltage on VDDQ relative to VSS: -0.5 ~ 3.6 V; (6)Output Short Circuit Current: 50 mA; (7)Power Dissipation: 1 W.

Features

HY5DV641622AT-36 features: (1)3.3V for VDD and 2.5V for VDDQ power supply; (2)All inputs and outputs are compatible with SSTL_2 interface; (3)JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch; (4)Fully differential clock inputs (CK, /CK) operation; (5)Double data rate interface; (6)Source synchronous - data transaction aligned to bidirectional data strobe (DQS); (7)x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O; (8)Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ); (9)Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe.