(China (Mainland))
Product Summary
The Hynix HY5DU561622ETP-J is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 16Mx16 DDR SDRAM HY5DU561622ETP-J offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
Parametrics
HY5DU561622ETP-J absolute maximum ratings: (1)Ambient Temperature: TA: 0~ 70 °C; (2)Storage Temperature: TSTG: -55 ~ 125 °C; (3)Voltage on Any Pin relative to VSS: VIN, VOUT: -0.5 ~ 3.6 V; (4)Voltage on VDD relative to VSS: VDD, VDDQ: -0.5 ~ 3.6 V; (5)Short Circuit Output Current: IOS: 50 mA; (6)Power Dissipation: PD: 1 W; (7)Soldering Temperature. Time: TSOLDER: 260. 10 °C. Sec.
Features
HY5DU561622ETP-J features: (1)2.5V +/-5% VDD and VDDQ power supply supports 250/200 Mhz; (2)2.6V +/- 0.1V VDD/VDDQ power supply supports 300/ 275Mhz; (3)2.8V +/- 0.1V VDD/ VDDQ power supply supports 350Mhz; (4)All inputs and outputs are compatible with SSTL_2 interface; (5)JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch; (6)Fully differential clock inputs (CK, /CK)operation; (7)Double data rate interface; (8)Source synchronous - data transaction aligned to bidirectional data strobe (DQS); (9)x16 device has 2 bytewide data strobes (LDQS, UDQS)per each x8 I/O.
Diagrams
