(China (Mainland))
Product Summary
The HY5DU28822AT-H is a 134,217,728-bit CMOS double data rate(DDR) synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The HY5DU28822AT-H offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), data, data strobes and write data masks inputs are sampled on both rising and falling edges of the HY5DU28822AT-H. The data path is internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
Parametrics
HY5DU28822AT-H absolute maximum ratings: (1)Ambient temperature TA: 0 ~ 70 ℃; (2)Storage temperature TSTG: -55 ~ 125 ℃; (3)Voltage on Any Pin relative to VSS VIN, VOUT: -0.5 ~ 3.6 V; (4)Voltage on VDD relative to VSS VDD: -0.5 ~ 3.6 V; (5)Voltage on VDDQ relative to VSS VDDQ: -0.5 ~ 3.6 V; (6)Output short circuit current IOS: 50 mA; (7)Power dissipation PD: 1 W; (8)Soldering temperature·time TSOLDER: 260 · 10 ℃ · sec.
Features
HY5DU28822AT-H features: (1)VDD, VDDQ = 2.5V +/- 0.2V; (2)All inputs and outputs are compatible with SSTL_2 interface; (3)Fully differential clock inputs (CK, /CK)operation; (4)Double data rate interface; (5)Source synchronous - data transaction aligned to bidirectional data strobe (DQS); (6)Data outputs on DQS edges when read (edged DQ)Data inputs on DQS centers when write (centered DQ); (7)On chip DLL align DQ and DQS transition with CK transition; (8)DM mask write data-in at the both rising and falling edges of the data strobe; (9)tRAS Lock-out function supported; (10)All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock; (11)Programmable /CAS latency 2 and 2.5 supported; (12)Programmable burst length 2 / 4 / 8 with both sequential and interleave mode; (13)Internal four bank operations with single pulsed /RAS; (14)Auto refresh and self refresh supported; (15)4096 refresh cycles / 64ms; (16)JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch; (17)Full and Half strength driver option controlled by EMRS.
Diagrams
