Product Summary

The HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. HY57V161610D is organized as 2banks of 524,288x16. The HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Parametrics

HY57V161610D absolute maximum ratings: (1)Ambient Temperature TA: 0 ~ 70 ℃; (2)Storage Temperature TSTG: -55 ~ 125 ℃; (3)Voltage on Any Pin relative to VSS VIN, VOUT: -1.0 ~ 4.6 V; (4)Voltage on VDD relative to VSS VDD: -1.0 ~ 4.6 V; (5)Short Circuit Output Current IOS: 50 mA; (6)Power Dissipation PD: 1 W; (7)Soldering Temperature·Time TSOLDER: 260 10 ℃ Sec.

Features

HY57V161610D features: (1)Single 3.0V to 3.6V power supply; (2)All device pins are compatible with LVTTL interface; (3)JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch; (4)All inputs and outputs referenced to positive edge of system clock; (5)Data mask function by UDQM/LDQM; (6)Internal two banks operation; (7)Auto refresh and self refresh; (8)4096 refresh cycles / 64ms; (9)Programmable Burst Length and Burst Type; (10)Programmable CAS Latency ; 1, 2, 3 Clocks.

Diagrams

HY57V161610D functional block diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)		 Quantity
HY57V161610D
HY57V161610D
Other

Data Sheet
Negotiable 
HY57V161610D-I
HY57V161610D-I
Other

Data Sheet
Negotiable