Product Summary

The ED5116AFTA-6B-E is a 512M bits Double Data Rate (DDR) SDRAM organized as 16,777,216 words × 8 bits × 4 banks and 8,388,608 words ×16 bits × 4 banks, respectively. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.

Parametrics

D5116AFTA-6B-E absolute maximum ratings: (1)Voltage on any pin relative to VSS VT: –1.0 to +3.6V; (2)Supply voltage relative to VSS VDD: –1.0 to +3.6V; (3)Short circuit output current IOS: 50mA; (4)Power dissipation PD: 1.0W; (5)Operating ambient temperature TA: 0 to +70℃; (6)Storage temperature Tstg: –55 to +125℃.

Features

D5116AFTA-6B-E features: (1)Double-data-rate architecture; two data transfers per clock cycle; (2)The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture; (3)Bi-directional data strobe (DQS) is transmitted/received with data for capturing data at the receiver; (4)Data inputs, outputs, and DM are synchronized with DQS; (5)DQS is edge-aligned with data for READs; center-aligned with data for WRITEs; (6)Differential clock inputs (CK and /CK); (7)DLL aligns DQ and DQS transitions with CK transitions; (8)Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS; (9)Data mask (DM) for write data.

Diagrams

D5116AFTA-6B-E pin connection