TSB43AB23PDTG4

TSB43AB23PDTG4, Link Layer Controller, ±20mA, -0.5 to +0.5V, QFP

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Price:: US $2.90~3.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
1 ~ 10 :	3.00 / Piece
20 ~ 100 :	2.90 / Piece

PartNumber:: TSB43AB23PDTG4

Brand:: Texas Instruments - TI | Pack: QFP | D/C: 09+

Availability:: Supply Ability: 1/Month Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

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Products Upload time: 2013-06-17

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Part Number:TSB43AB23PDTG4
US $2.90 - 3.00
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Product Summary

The TSB43AB23PDTG4 is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC). It is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification. It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB23PDTG4 device provides three 1394 ports that have separate cable bia (TPBIAS). It also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.

Parametrics

TSB43AB23PDTG4 absolute maximum ratings: (1)Input voltage range for PCI, VI, PHY, and Miscellaneous: -0.5 to VDD +0.5V; (2)Output voltage range for PCI, VO, PHY, and Miscellaneous: -0.5 to VDD +0.5V; (3)Input clamp current: ±20mA; (4)Output clamp current: ±20 mA; (5)Electrostatic discharge : HBM:2kV; (6)Operating free-air temperature: 0℃ to 70℃; (7)Storage temperature range: -65℃ to 150℃; (8)Lead temperature 1,6 mm (1/16 inch) from cage for 10 seconds: 260℃.

Features

TSB43AB23PDTG4 features: (1)Fully interoperable with FireWire and i.LINK implementations of IEEE Std 1394; (2)Compliant with Intel Mobile Power Guideline 2000; (3)Cable ports monitor line conditions for active connection to remote node; (4)Cable power presence monitoring; (5)Separate cable bias (TPBIAS) for each port; (6)Low-cost 24.576-MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s; (7)Fabricated in advanced low-power CMOS process; (8)Isochronous receive dual-buffer mode; (9)Out-of-order pipelining for asynchronous transmit requests.