(China (Mainland))
Product Summary
The NT5SV4M16DT-7K is a four-bank synchronous DRAM. It organized as 4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and 1Mbit x 16 I/O x 4 Bank, respectively. The NT5SV4M16DT-7K achieve high-speed data transfer rates of up to 200MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with NTCs advanced 64Mbit single transistor CMOS DRAM process technology. The NT5SV4M16DT-7K is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock.
Parametrics
NT5SV4M16DT-7K absolute maximum ratings: (1)Power supply voltage: -0.3 to +4.6 V; (2)Power supply voltage for output: -0.3 to +4.6 V; (3)Input voltage: -0.3 to VDD+0.3 V; (4)Output voltage: -0.3 to VDD+0.3 V; (5)Operating temperature (ambient): 0 to +70 °C; (6)Storage temperature: -55 to +125 °C; (7)Power dissipation: 1.0 W; (8)Short circuit output current: 50 mA.
Features
NT5SV4M16DT-7K features: (1)Single pulsed RAS interface; (2)Fully synchronous to positive clock edge; (3)Four banks controlled by BS0/BS1 (Bank Select); (4)Programmable CAS latency: 2, 3; (5)Programmable burst length: 1, 2, 4, 8, full page; (6)Programmable wrap: Sequential or interleave; (7)Multiple burst read with single write option; (8)Automatic and controlled precharge command; (9)Data mask for read/write control (x4, x8); (10)Dual data mask for byte control (x16); (11)Auto refresh (CBR)and self refresh; (12)Suspend mode and power down mode; (13)Standard power operation; (14)4096 refresh cycles/64ms; (15)Random column address every CK (1-N Rule); (16)Single 3.3V ± 0.3V power supply; (17)LVTTL compatible; (18)Package: 54-pin 400 mil TSOP-Type II.
Diagrams
