(China (Mainland))
Product Summary
The MT48LC8M16A2P-6AG is a high-speed CMOS, dynamic random access memory. It contains 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4,096 rows by 2,048 columns by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4,096 rows by 1,024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4,096 rows by 512 columns by 16 bits.
Parametrics
MT48LC8M16A2P-6AG absolute maximum ratings: (1)Voltage on VDD/VDDQ supply relative to VSS: -1V +4.6V; (2)Voltage on inputs, NC or I/O pins relative to VSS: -1V +4.6V; (3)Operating temperature: TA (commercial): 0℃ +70℃, TA (industrial) –40℃ +85℃, TA (automotive): –40℃ +105℃; (4)Storage temperature (plastic): –55℃ +150℃; (5)Power dissipation: 1W.
Features
MT48LC8M16A2P-6AG features: (1)PC100- and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge ; (5)Programmable burst lengths (BL): 1, 2, 4, 8, or full page; (6)Auto precharge, includes concurrent auto precharge, and auto refresh modes; (7)Self refresh mode; standard and low power; (8)64ms, 4,096-cycle refresh (commercial & industrial); (9)16ms, 4,096-cycle refresh (Automotive); (10)LVTTL-compatible inputs and outputs; (11)Single +3.3 ±0.3V power supply.
Diagrams
