(China (Mainland))
Product Summary
The HY57V643220DTP-7 is a 67,108,864bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. The HY57V643220DTP-7 is organized as 4banks of 524,228*32. The HY57V643220DTP-7 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Parametrics
HY57V643220DTP-7 absolute maximum ratings: (1)Ambient Temperature, TA: -40 ~ 85℃; (2)Storage Temperature, TSTG: -55 ~ 125℃; (3)Voltage on Any Pin relative to VSS, VIN, VOUT: -1.0 ~ 4.6 V; (4)Voltage on VDD relative to VSS, VDD: -1.0 ~ 4.6 V; (5)Voltage on VDDQ relative to VSS, VDDQ: -1.0 ~ 4.6 V; (6)Short Circuit Output Current, IOS: 50 mA; (7)Power Dissipation, PD: 1 W.
Features
HY57V643220DTP-7 features: (1)Voltage : VDD, VDDQ 3.3V supply voltage; (2)All device pins are compatible with LVTTL interface; (3)JEDEC standard 400mil 86pin TSOP-II with 0.5mm of pin pitch ; (4)All inputs and outputs referenced to positive edge of system clock; (5)Data mask function by DQM 0, 1, 2 and DQM 3; (6)Internal four banks operation; (7)Auto refresh and self refresh; (8)4096 Refresh cycles / 64ms ; (9)Programmable Burst Length and Burst Type; (10) Programmable CAS Latency ; 2, 3 Clocks; (11)Burst Read Single Write operation.
Diagrams
