(China (Mainland))
Product Summary
The HY57V641620HGLT-P is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications r which require low power consumption and extended temperature range. HY57V641620HG is organized as 4banks of 1,048,576x16. HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Parametrics
HY57V641620HGLT-P maximum ratings: (1)Ambient Temperature TA: -40 ~ 85 °C; (2)Storage Temperature TSTG: -55 ~ 125 °C; (3)Voltage on Any Pin relative to VSS VIN, VOUT: -1.0 ~ 4.6 V; (4)Voltage on VDD relative to VSS VDD, VDDQ: -1.0 ~ 4.6 V; (5)Short Circuit Output Current IOS: 50 mA; (6)Power Dissipation PD: 1 W; (7)Soldering Temperature ⋅ Time TSOLDER: 260 ⋅ 10 °C ⋅ Sec.
Features
HY57V641620HGLT-P features: (1)Single 3.3±0.3V power supply Note); (2)All device pins are compatible with LVTTL interface; (3)JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch; (4)All inputs and outputs referenced to positive edge of system clock; (5)Data mask function by UDQM or LDQM; (6)Internal four banks operation; (7)Auto refresh and self refresh; (8)4096 refresh cycles / 64ms; (9)Programmable Burst Length and Burst Type; (10)Programmable CAS Latency; 2, 3 Clocks.
Diagrams
