(China (Mainland))
Product Summary
The HY57V283220TP-6 is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. The HY57V283220TP-6 is organized as 4banks of 1,048,576x32. The HY57V283220TP-6 is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Parametrics
HY57V283220TP-6 absolute maximum ratings: (1)Ambient Temperature TA: 0 ~ 70 °C; (2)Storage Temperature TSTG: -55 ~ 125 °C; (3)Voltage on Any Pin relative to VSS VIN, VOUT: -1.0 ~ 4.6 V; (4)Voltage on VDD relative to VSS VDD, VDDQ: -1.0 ~ 4.6 V; (5)Short Circuit Output Current IOS: 50 mA; (6)Power Dissipation PD: 1 W.
Features
HY57V283220TP-6 features: (1)JEDEC standard 3.3V power supply; (2)All device pins are compatible with LVTTL interface; (3)86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch; (4)All inputs and outputs referenced to positive edge of system clock; (5)Data mask function by DQM0,1,2 and 3; (6)Internal four banks operation; (7)Auto refresh and self refresh; (8)4096 refresh cycles / 64ms; (9)Programmable Burst Length and Burst Type.
Diagrams
