(China (Mainland))
Product Summary
The hy57v281620at-p is a 134,217,728 bit CMOS Synchronous DRAM. The hy57v281620at-p is ideally suited for the main memory applications which require large memory density and high bandwidth. The hy57v281620at-p is organized as 4banks of 2,097,152x16. The hy57v281620at-p is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs of the hy57v281620at-p are synchronized with the rising edge of the clock input. The data paths of the hy57v281620at-p are internally pipelined to achieve very high bandwidth. All input and output voltage levels of the hy57v281620at-p are compatible with LVTTL.
Parametrics
hy57v281620at-p absolute maximum ratings: (1) Ambient Temperature TA: 0 to 70°C; (2) Storage Temperature TSTG: -55 to 125°C; (3) Voltage on Any Pin relative to VSS VIN, VOUT: -1 to 4.6V; (4) Voltage on VDD relative to VSS, VDD, VDDQ: -1 to 4.6V; (5) Short Circuit Output Current IOS: 50mA; (6) Power Dissipation PD: 1W; (7) Soldering Temperature Time TSOLDER: 260°C, 10 Sec.
Features
hy57v281620at-p features: (1) Single 3.3±0.3V power supply; (2) All device pins are compatible with LVTTL interface; (3) JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch; (4) All inputs and outputs referenced to positive edge of system clock; (5) Data mask function by UDQM or LDQM; (6) Internal four banks operation; (7) Auto refresh and self refresh; (8) 4096 refresh cycles / 64ms; (9) Programmable Burst Length and Burst Type; (10) Programmable CAS Latency ; 2, 3 Clocks.
Diagrams
