(China (Mainland))
Product Summary
The 29F200BC-70PFTN is a 2M-bit, 5.0 V-only Flash memory organized as 256K bytes of 8 bits each or 128K words of 16 bits each. The 29F200BC-70PFTN is offered in a 48-pin TSOP and 44-pin SOP packages. This device is designed to be programmed in-system with the standard system 5.0 V VCC supply. 12.0 V VPP is not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. The standard 29F200BC-70PFTN offers access times 55 ns and 90 ns allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write enable (WE), and output enable (OE) controls.
Parametrics
29F200BC-70PFTN absolute maximum ratings: (1)Storage Temperature: –55°C to +125°C; (2)Ambient Temperature with Power Applied: –40°C to +85°C; (3)Voltage with respect to Ground All pins except A9, OE, RESET (Note 1): –2.0 V to +7.0 V; (4)VCC (Note 1): –2.0 V to +7.0 V; (5)A9, OE, RESET (Note 2): –2.0 V to +13.5 V.
Features
29F200BC-70PFTN features: (1)Single 5.0 V read, write, and erase: Minimizes system level power requirements; (2)Compatible with JEDEC-standard commands: Uses same software commands as E2PROMs; (3)Compatible with JEDEC-standard world-wide pinouts: 48-pin TSOP (Package suffix: PFTN – Normal Bend Type, PFTR – Reversed Bend Type);; (4)44-pin SOP (Package suffix: PF); (5)Minimum 100,000 write/erase cycles; (6)High performance; (7)Sector erase architecture: One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes.; (8)Any combination of sectors can be concurrently erased. Also supports full chip erase.; (9)Boot Code Sector Architecture: T = Top sector; B = Bottom sector; (10)Embedded EraseTM Algorithms; (11)Automatically writes and verifies data at specified address; (12)Data Polling and Toggle Bit feature for detection of program or erase cycle completion; (13)Ready/Busy output (RY/BY); (14)Hardware method for detection of program or erase cycle completion; (15)Low Vcc write inhibit ≤ 3.2.
Diagrams
